1. Field of the Invention
The present invention relates to a barrel shifter having a CMOS structure characterized by the layout pattern of the MOS integrated circuit.
2. Description of the Related Art
When the digital data is shift-operated in a logic circuit, basically it is possible to shift an optional number of bits by repetitively using the 1-bit shifter. However, for the hardware to execute such shifting at high speed, a barrel shifter is used, which can shift-operate an optional number of bits in one operation using a matrix type multiplexer.
For one example of the barrel shifter, description will be made on a barrel shifter in the 5.times.5 (n.times.n) bit configuration which is applied for the digital data of 5 (=n) bit data width.
FIG. 1 shows a schematic diagram showing the state of each bit when a 5-bit input data DI(0:4)="1000" is moved rightward by 2 bits by a barrel shifter of 5.times.5 bit configuration. In this example, output data DO(0:4)="00100" is obtained, wherein each bit of the input data DI(0:4)="1000" in which only MSB is "1" and other 4 bits are all "0" is moved rightward, that is, to the LSB side by 2 bits.
When a barrel shifter assembled into, for example, a one-chip microprocessor is realized as one example of MOS integrated circuits, conventionally NMOS structure comprising only N-type transfer gates has been generally employed. The main reason for this is that the N-type transfer gate has an advantage of high area efficiency because it needs only a small installation space when it is arranged on a semiconductor chip as compared with P-type transfer gate.
However, in the NMOS-structure circuit, it is necessary to add a pull-down circuit to load the initial data onto the input and output buses, and consequently, a wait time is required before the initial data is loaded for operation. In addition, in such a circuit in which initial data must be loaded, there is no problem when clock frequency is high, but when it is low, current leaks and data is not held correctly, generating a problem of limiting the operating frequency.
FIG. 2 is a truth table when the 5.times.5 bit barrel shifter is realized by COMS configuration as described above, while FIG. 3 is a schematic diagram showing CMOS transfer gates of 5.times.5 bit configuration barrel shifter as hardware that realizes such logics as well as wiring condition of data lines and control signal lines.
SFT shown in FIG. 2 shows the number of shift bits, and in actual hardware, positive logic N type transfer gate control signal S(0:4) and negative logic P type transfer gate control signal #S(0:4) are generated by a decoder from the signal indicating the shift bit number SFT. And turning ON/OFF of each transfer gate in accordance with the levels of these transfer gate control signal S(0:4) and #S(0:4), the output data DO(0:4) is obtained from the input data DI(0:4) shifted by the number of bits indicated by the shift bit number SFT.
In FIG. 3, reference symbols T00, T10 . . . T44 show CMOS type transfer gates. In the barrel shifter of 5.times.5 bit configuration, 25 pieces of CMOS type transfer gate Tij (however, i=0 to 4, j=0 to 4) are, in actuality, arranged in the form of matrix. And to these CMOS type transfer gates Tij, the first group data lines L10, L11 to L14 (L01 to L04) and the second group data lines L20 to L24 as well as control signal lines S0 to S4, #S0 to #S4 are wired.
The first group data lines L10, L11 to L14 (L01 to L04) are wired as follows.
Data line L10 is connected to CMOS type transfer gates T00, T11, T22, T33 and T44 in the form of steps.
Data line L11 is connected to CMOS type transfer gates T10, T21, T32 and T43 in the form of steps, and data line L01 is connected to CMOS transfer gate T04 in the form of steps.
Data line L12 is connected to CMOS type transfer gates T20, T31 and T42 in the form of steps, and data line L02 is connected to CMOS transfer gates T03 and T14 in the form of steps.
Data line L13 is connected to CMOS type transfer gates T30 and T41 in the form of steps, and data line L03 is connected to CMOS transfer gates T02, T13 and T24 in the form of steps.
Data line L14 is connected to CMOS type transfer gate T40 in the form of steps, and data line L04 is connected to CMOS transfer gates T01, T12, T23 and T34 in the form of steps.
The second group data lines L20 to L24 are wired as follows. Data line L20 of the second group is connected to CMOS type transfer gates T00, T01, T02, T03 and T04 in a straight line, data line L21 to CMOS type transfer gates T10, T11, T12, T13 and T14 in a straight line, data line L22 to CMOS type transfer gates T20, T21, T22, T23 and T24 in a straight line, data line L23 to CMOS type transfer gates T30, T31, T32, T33 and T34 in a straight line, and data line L24 to CMOS type transfer gates T40, T41, T42, T43 and T44 in a straight line.
On the other hand, control signals S0, #S0 corresponding to the shift bit number 0 are connected to CMOS type transfer gates T00, T10, T20, T30 and T40 in a straight line, control signals S1, #S1 corresponding to shift bit number 1 to CMOS type transfer gates T01, T11, T21, T31 and T41 in a straight line, control signals S2, #S2 corresponding to shift bit number 2 to CMOS type transfer gates T02, T12, T22, T32 and T42 in a straight line, control signals S3, #S3 corresponding to shift bit number L3 to CMOS type transfer gates T03, T13, T23, T33 and T43 in a straight line, and control signals S4, #S4 corresponding to shift bit number 4 to CMOS type transfer gates T04, T14, T24, T34 and T44 in a straight line.
In this kind of barrel shifter, when the 5-bit input data DI(0:4) is shifted, for example, rightward by k (k=0 to 4) bits, control signals Sk, #Sk are made active (Sk="1", #Sk="0") and each bit of input data DI(0:4) is inputted to data lines L10, L11 to L14 (L01 to L04) of the first group. Then, of 25 CMOS type transfer gates, 5 COMS type transfer gates Tik in the longitudinal direction in FIG. 3 turn 0N and the remaining 20 COMS type transfer gates turn OFF. Thereby, output data DO(0:4) obtained by shifting input data DI(0:4) rightward by k bits is outputted from data lines L20 to L24 of the second group.
Conversely, when the 5-bit input data DI(0:4) is shifted leftward by k (k=0 to 4) bits, control signals Sk, #Sk are made active (Sk="1", #Sk="0") and each bit of input data DI(0:4) is inputted to data lines L20 to L24 of the second group. Then, of 25 CMOS type transfer gates, 5 COMS type transfer gates Tik in the longitudinal direction in FIG. 3 turn ON and the remaining 20 COMS type transfer gates turn OFF. Thereby, output data DO(0:4) obtained by shifting input data DI(0:4) leftward by k bits is outputted from data lines L10, L11 to L14 (L01 to L04) of the first group.
Now, the barrel shifter having a CMOS structure will be described in detail hereinafter. FIG. 4 is a logic circuit diagram indicating part of logic configuration when the barrel shifter of 5.times.5 bit configuration shown in FIG. 3 as described above is configured with COMS transfer gates, while FIG. 5 is a schematic diagram showing the layout of the COMS type transfer gates on a chip.
In this embodiment, as one example, description will be made on the case when 5-bit input data DI(0:4) is designated by "0011" and is shifted rightward by 2 bits (hereinafter called "right 2-bit shift"). FIG. 4 and FIG. 5 show T31, T32, T41 and T42 of CMOS type transfer gates which configure the barrel shifter shown in FIG. 3.
In the range shown in FIG. 5, for example, control signal S1 for N type transfer gates is connected to gates, that is, control terminals of N type transfer gates N31, N41 of CMOS type transfer gates T31, T41, while control signal #S2 for P type transfer gate is connected to gates, that is, control terminals of P type transfer gates P32, P42 of CMOS type transfer gates T32, T42.
Data line L12 of the first group is connected to controlled terminals, that is, sources or drains of P-type transfer gate P31 and N-type transfer gate N31 of CMOS type transfer gate T31, and N-type transfer gate N42 and P-type transfer gate P42 of CMOS type transfer gate T42. Data line L24 of the second group is connected to controlled terminals, that is, sources or drains of P-type transfer gate P41 and N-type transfer gate N41 of CMOS type transfer gate T41, and N-type transfer gate N42 and P-type transfer gate P42 of CMOS type transfer gate T42.
In FIG. 5, in case of right shift, that is, in the case where the input data is inputted from the data lines L10, L11 to L14 (L01 to L04) of the first group and the output data is outputted to the data lines L20 to L24 of the second group, the drain of each N-type and P-type transfer gate becomes ".times." and the source ".largecircle." respectively. Conversely, in case of left shift, that is, in the case where when the input data is inputted from the data lines L20 to L24 of the second group and the output data is outputted to the data lines L10, L11 to L14 (L01 to L04) of the first group, the drain of each N-type and P-type transfer gate becomes ".largecircle." and the source ".times." respectively.
In case of right 2-bit shift, as shown in FIG. 2, because S2 among the control signals S0 to S4 for N-type transfer gate and #S2 among the control signals #S0 to #S4 for P-type transfer gate become active (S2="1", #S2="0") in FIG. 4 and FIG. 5, CMOS type transfer gate T42 (composed of P-type transfer gate P42 and N-type transfer gate N42 in FIG. 5) for 2-bit shift connected to data line L24 of the second group and, in the same manner, CMOS type transfer gate T32 (composed of P-type transfer gate P32 and N-type transfer gate N32 in FIG.5) for 2-bit shift connected to data line L23, turn on.
And each bit of input data DI(0:4) is inputted to data the lines L10, L11 to L14 (L01 to L04) of the first group, but in the range shown in FIG. 5, input data DI(2) is inputted to the data line L12 and input data DI(3) to the data line L13, respectively. This causes the data "0" of DI(1) of the input data DI(0:4) to propagate to the data line L23 via the CMOS type transfer gate T32 from the data line L11, and in the same manner, the data "1" of DI(2) to the data line L24 via the CMOS type transfer gate T42 from the data line L12.
The circuit of CMOS structure described above as shown in FIG. 4 and FIG. 5, unlike the barrel shifter having a NMOS structure, requires no structure for loading the initial data and is operable from high frequency to clock stop condition. However, the CMOS structure, for example, CMOS type transfer gates T31, T32, T41, T42, etc. shown in FIG. 4 comprises both P-type and N-type transfer gates P31 and T31, P32 and T32, P41 and T41, and T42 and T42, etc., respectively, requiring a large layout area on the chip, increasing product costs. The layout area is further increased because the output capacity of the transfer gate for drain output data line is large and wiring of gate control signals for control of the number of shift bits is longer because it makes a detour around the transfer gate.
Under these circumstances, barrel shifters having a CMOS structure have not yet been put into practical use for industrial products. However, as described above, the CMOS structure circuit requires no circuit for loading the initial data and has such an ideal advantage of reducing electric consumption as that it is operable from high frequency to clock stop condition. This is extremely advantageous for so-called lap top type or palm top type microcomputers which operate primarily from a battery.
The object of the present invention is to provide a barrel shifter having a CMOS structure integrated on MOS integrated circuits, which solves the above-mentioned problems, requires a small layout area, and is capable of carrying out high-speed shift operation so as to put the barrel shifter having a CMOS structure into practical use while making the best use of its advantages of no need for a circuit for loading the initial data and capabilities to make static operation and to operate from high frequency to clock stop condition.